1. Technical Field
Embodiments of the present invention relate to a semiconductor memory device which stores data of various widths, which is capable of compensating for delay time variations between input data bits when processing multi-bit data.
2. Description of the Related Art
Semiconductor memory devices are capable of simultaneously processing multi-bit data using a single semiconductor chip. An example of this type of device is a YDRAM (Yellowstone Dynamic Random Access Memory). Processing multi-bit data means that a single semiconductor chip can simultaneously support X16, X8, X4, X2 and X1 data modes. Supporting an X16 mode means that a semiconductor memory device can receive and process 16 bits of data at a time. Likewise, supporting an X1 mode means that a semiconductor memory device can receive and process one bit of data at a time. In a semiconductor memory device capable of simultaneously processing multi-bit data, the propagation delay time of input data is longer when the semiconductor memory device operates in a X1 mode than when the device operates in a X16 mode. This deteriorates the timing margin of the flip-flops that receive the data.
FIGS. 1(a), (b), (c), (d) and (e) illustrate a semiconductor memory device operating in an X16 mode, X8 mode, X4 mode, X2 mode and X1 mode, respectively. The numerals shown in FIG. 1 denote pin numbers of the semiconductor memory device. If the semiconductor memory device operates in the X16 mode, as shown in FIG. 1(a), data is input into each of the 16 pins and the input data is applied to an internal circuit (not shown) from each pin.
In FIG. 1(a), td1 denotes the period of time required for data outputted from each pin of the semiconductor memory device to be delivered to an input buffer (not shown) of the internal circuit (not shown). If a semiconductor memory device operates in the X1 mode, as shown in FIG. 1(e), data is input to one of 16 pins of the semiconductor memory device (pin 0 in this case) and the input data is transmitted from the pin 0 to the internal circuit (not shown). Considering an internal circuit that is located the furthest distance from the pin 0, the period of time required for data output from the pin 0 of the semiconductor memory device operating in X1 mode to be transmitted to the input buffer (not shown) of the internal circuit (not shown) is represented by td2+td3.
As described above, the period of time required for data to be applied to the input buffer (not shown) (i.e. propagation time), largely depends on whether the semiconductor memory device operates in the X16 mode or the X1 mode. Since the frequency of a reference clock signal for operating the semiconductor memory device does not depend on whether the semiconductor memory device operates in the X16 mode or in the X1 mode, the margin of the input data may be poor, and the set-up and hold time characteristics of the input data may deteriorate due to a long propagation delay time. The propagation delay time may vary with the position of the internal circuit of the semiconductor memory device, even in the same operating mode. Referring to FIG. 1(e), the period of time required for the data to be input into the input buffer (not shown) of the internal circuit (not shown) located the furthest distance from the pin 0 is td2+td3. However, the period of time required for the data to be transmitted to the input buffer (not shown) of the internal circuit (not shown) having the shortest distance from the pin 0 is td4.
As described above, the time required for the data to be applied to the input buffer (not shown) of the internal circuit (not shown) (i.e., the propagation delay time), may vary according to the position of the internal circuit, even when the semiconductor memory device operates in the same operating mode. Because a reference clock signal for operating the semiconductor memory device has a specific frequency that does not vary in the same operating mode, the margin of the input data may become poor and the set-up and hold time characteristics of the input data may deteriorate due to a long propagation delay time.
FIG. 2 shows a portion of a semiconductor memory device for illustrating the propagation time difference, with reference to FIG. 1. FIG. 3 is a timing diagram illustrating the operation of the semiconductor memory device shown in FIG. 2.
Referring to FIG. 2, the semiconductor memory device 200 includes flip-flops FF11, FF21, FFn1, FF12, FF22, FFn2, FF13, FF23 and FFn3 that receive and store first to nth data bits D<1>, D<2>, . . . , D<n>. The flip-flips FF11, FF21, FFn1, FF12, FF22, FFn2, FF13, FF23 and FFn3 store the first to nth data bits D<1>, D<2>, . . . , D<n>in response to a reference clock signal REFCK. D1_1, D2_1 and Dn_1 denote data contents that result from delay of the first to nth data D<1>, D<2>, . . . , D<n> for different periods of time. The data bits D1_1, D2_1 and Dn_1 are input into the flip-flops FF11, FF21 and FFn1, located at a first stage. Reference numerals t1, t2 and tn respectively represent periods of time required for the first to nth data bits D<1>, D<2>, . . . , D<n> to be input into the flip-flops FF11, FF21 and FFn1 at the first stage.
The second data bit D<2> takes the shortest amount of time to arrive at the flip-flop FF21 and the nth data D<n> takes the longest amount of time to reach the flip-flop FFn1. The period of time required by the first data D<1> to be input into the flip-flop FF11 is in-between the time periods required for the second data D<2> and the nth data bit D<n>. The data bits D<1>, D<2>, . . . , D<n> require different time periods to be input into the flip-flops FF11, FF21 and FFn1, located at the first stage in the semiconductor memory device 200, because data input pins (not shown) have different distances from the flip-flops FF11, FF21 and FFn1, as illustrated in FIG. 1. The time periods required for the data bits D<1>, D<2>, . . . , D<n> to be input into the flip-flops FF11, FF21 and FFn1 may vary in different operating modes of the semiconductor memory device, such as the X16 mode and the X1 mode.
FIG. 3 shows delay time t1 of the first data bit D<1>, delay time t2 of the second data bit D<2>, and delay time tn of the nth data bit D<n>, corresponding to data waveforms. In FIG. 3, the uppermost waveform illustrates the first to nth data bits D<1>, D<2>, . . . , D<n> having the same delay time and being simultaneously applied to the first-stage flip-flops FF11, FF21 and FFn1. It can be seen from FIG. 3 that the nth data bit Dn_1 with the longest delay time has the shortest set-up time Sn, and the second data D2_1 with the shortest delay time has the longest set-up time S2. If there is a delay time difference among the data contents, data having long delay times will not be able to be stored in a corresponding flip-flop, in response to the reference clock signal REFCK. Likewise, data having short delay times may have no difficulty in being stored in a corresponding flip-flop, in response to the reference clock signal REFCK.
So, the propagation delay time of the data may become problematic in the front-stage flip-flops FF11, FF21 and FFn1 of the semiconductor memory device 200. That is, if the data is properly stored in the front flip-flops FF11, FF21 and FFn1 based on a single reference clock signal REFCK pulse, even though the data bits have different propagation delay time intervals, the data output from the flip-flops FF11, FF21 and FFn1 may then be stored in the flip-flops FF12, FF22 and FFn2 at the next stage, in response to a subsequent the reference clock signal REFCK pulse without any problem.
FIG. 4A is a timing diagram illustrating the case where there is a small propagation delay time difference between all data bits input to the semiconductor memory device of FIG. 2. FIG. 4B is a timing diagram illustrating a case where there is a large propagation delay time difference between at least some of the data bits input to the semiconductor memory device of FIG. 2.
Referring to FIG. 4A, when the first to nth data bits (D<1> to D<n>) all have small propagation delay time differences, all of the data bits can be stored in the flip-flops FF11, FF21 and FFn1 at the first stage, although they have different set-up and hold time characteristics. In contrast, as shown in FIG. 4B, however, when at least some of the first to nth data bits (D<1> to D<n>) have a large propagation delay time difference, even though the first and second data D<1> and D<2> are stored in the corresponding front flop-flops FF11 and FF21 in response to the reference clock signal REFCK, at least the nth data D<n> cannot be stored in the front flip-flop FFn1 in response to the reference clock signal REFCK because of its long propagation delay time.
As described above, all of data contents cannot be latched using a single reference clock signal REFCK when the propagation delay time of multi-bit data input into the semiconductor memory device 200 is increased and the propagation delay time difference among multi-bit data contents becomes large.
Accordingly, it would be desirable to provide a semiconductor memory device capable of compensating for delay time differences in multi-bit data input to a memory device. by adjusting the magnitude of delay of a reference clock signal for controlling flip-flops of a front stage.
According to one aspect of the present invention, a semiconductor memory device includes first and second data storage units. The first data storage unit stores first to nth data input into the first data storage unit, in response to a latch clock signal. The second data storage unit stores the first to nth data output from the first data storage unit, in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch clock signals. The first to nth sub latch clock signals are generated at different points in time, according to propagation delay time periods of the first to nth data contents that respectively correspond to the first to nth sub latch clock signals. The first data storage unit includes first to nth storage elements which store the first to nth data, in response to the respective first to nth sub latch clock signals.
The first to nth programmable delays delay the reference clock signal to generate the respective first to nth sub latch clock signal. The first to nth programmable delays determine the delay time of the reference clock signal, according to propagation delay time periods of the first to nth data applied to the first to nth programmable delays. In embodiments, the first to nth programmable delays determine degrees of delaying the reference clock signal for generating the first to nth sub latch clock signals, according to a fuse option. In embodiments, the first to nth programmable delays determine degrees of delaying the reference clock signal for generating the first to nth sub latch clock signals, according to MRS (Mode Register Set). The number of bits of data input into the semiconductor memory device may be selected according to the operation mode of the semiconductor memory device.
According to another aspect of the present invention, a semiconductor memory device is compensating delay time of multi-bit data, which has a plurality of data paths for receiving data. Each of the plurality of data paths include a plurality of data storage units for storing input data. The first data storage units of the plurality of data paths store the data in response to a latch clock signal. Data storage units (other than the first data storage units) store the data output from the first data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal may include as many sub latch clock signals as the number of data paths. The sub latch clock signals are generated at different points of time according to propagation delay time of the data input into the corresponding data paths.
The semiconductor memory device may include a plurality of programmable delays which delay the reference clock signal to generate the sub latch clock signals. The plurality of programmable delays determine delay time of the reference clock signal according to propagation delay time of the data input to a corresponding data path. In embodiments, the programmable delays determine degrees of delaying the reference clock signal for generating the sub latch clock signals, according to a fuse option. In embodiments, the programmable delays determine degrees of delaying the reference clock signal for generating the first to nth sub latch clock signals, according to a MRS (Mode Register Set). The number of data paths for receiving data can be selected according to the operation mode of the semiconductor memory device.
According to yet another aspect of the present invention, a semiconductor memory device compensates delay time of multi-bit data, which has a plurality of data paths for receiving data, in which each of the plurality of data paths includes a plurality of data storage units for storing input data. The first data storage units of the plurality of data paths operate asynchronously, while other data storage units operate synchronously. The first data storage units store the data in response to a latch clock signal. The other data storage units store the data output from the first data storage units in response to a reference clock signal. The sub latch clock signal is obtained by delaying the reference clock signal. The sub latch clock signals are generated at different of times according to propagation delay time of the data input into a corresponding data path.
The semiconductor memory device may include a plurality of programmable delays for delaying the reference clock signal to generate the sub latch clock signals. The plurality of programmable delays determine delay time of the reference clock signal according to propagation delay time of the data input into a corresponding data path. In embodiments, the programmable delays determine degrees of delaying the reference clock signal for generating the sub latch clock signals, according to a fuse option. In embodiments, the programmable delays determine degrees of delaying the reference clock signal for generating the first to nth sub latch clock signals, according to MRS (Mode Register Set). The number of data paths for receiving data may be selected according to the operation mode of the semiconductor memory device.